1. Field of the Invention
The present invention relates to a solid state relay circuit arrangement, for audio signals, of the type comprising a first MOSFET and a second MOSFET in a back-to-back configuration, adapted to receive an input signal on the source electrode of the first MOSFET and to take the output signal on the source electrode of the second MOSFET, with a driving voltage being applied to the gate electrodes of said first MOSFET and second MOSFET, apt to change, on the basis of its value, the operational state of said first MOSFET and second MOSFET.
2. Description of the Related Art
Often in audio systems, it is required to operate a switching between input audio signals towards an output, such as a speaker. For example, in the automotive sector Telematic Control Units (TCU) are known, in which it is required to switch the audio path from the external audio module to the internal audio amplifier, which becomes active during e-Call type voice communications.
The usual solution to implement the audio switch is to use a relay to switch the audio path. This component, in electromechanical form, presents several drawbacks in terms of reliability, oxidation of the contacts, minimum current problems (wetting current), the contact resistance in the presence of low amplitude signals and cost.
Solid State Relays (SSR) are components frequently used for switching because, compared to electromechanical relays, they are not affected by the disadvantages outlined above.
A solid state relay arrangement of known type used in analog power switches is that shown in FIG. 1, where a solid state relay arrangement 10 comprises a pair of MOSFET transistors, a first MOSFET transistor M1 and a second MOSFET transistor M2, connected in the configuration known as “back-to-back” or rather, through their respective drain electrodes D1, D2. A source electrode S1 of the first MOSFET M1 receives an input signal Vs1, for example an audio signal, from an input signal generator 21 and this first MOSFET M1 presents a first zener-type diode 24 connected between the source electrode S1 and its gate electrode G1, to protect the gate from ESD (Electrostatic Discharge).
Similarly, the second MOSFET M1 has a source electrode S2 on which a voltage signal Vs2 is formed, to which the output is connected, or rather a speaker 22. This second MOSFET M2 presents a second zener diode 26, connected between the source electrode S2 and a gate electrode G2.
The gates G1 and G2 of the MOSFETs M1 and M2 are connected to a driving voltage generator 30, or polarization voltage, comprising a driving series impedance 29, which generates a driving voltage Vbias on a driving node P downstream of the series impedance 29. As discussed further below, the voltage on the driving node P is used to control the operating states of the MOSFETs M1, M2, in particular between the ON state, the OFF state and the ohmic region. Numeral 35 in FIG. 1 indicates a ground reference.
In this case, to turn on the MOSFET M1, that is, to take it to the ON state, it is necessary that the driving voltage Vbias is:Vbias≧Vs1_max+Vgs1_th where Vs1_max indicates the maximum voltage on the source S1 and VgS1_th indicates the threshold gate-source voltage of the first MOSFET M1. The first MOSFET M1 then enters into the ohmic region of its characteristic function if:Vbias>>Vs1_max 
Similar considerations are valid for the second MOSFET M2, for which the ohmic region is only reached if:Vds_M2≦Vgs2−Vgs2_th where Vds_M2 is its drain-source voltage, while Vgs2 indicates the gate-source voltage, and Vgs2_th is the threshold voltage. This condition implies that the second MOSFET M2 only enters into the ohmic region if:Vbias>>Vs1_max 
In FIG. 2, a waveform of the input signal is shown Vs1, for example an audio signal, with a sinusoidal trend, as a function of the time t, having an amplitude A, and offset voltage Voff.
With an input signal Vs1 such as the signal shown in FIG. 2, the minimum driving voltage Vbias able to drive the MOSFETs M1 and M2 into the ohmic region for the entire period of the input waveform of FIG. 2 is:Vbias≧(VOFF+A)+Vgs_th 
With the solid state relay topology 10 shown in FIG. 1, the driving voltage must be greater than the maximum peak voltage Vpeak_max of the input signal Vs1, with the aim of guaranteeing the good conduction of the MOSFETs M1 and M2. In fact, for the maximum peak voltage Vpeak_max:Vpeak_max=Voff+A it is, in fact:Vbias≧Vpeak_max+Vgs1,2_th where Vgs1,2_th indicates the gate-source threshold voltage of the first or the second MOSFET, which are assumed equal.
Furthermore, in the circuit arrangement 10 of FIG. 1, the voltages between gate and source Vgs1,2 of the MOSFETs M1 and M2 vary with the amplitude A of the signal, maintaining the form of the signal, so that if the input signal Vs1 is sinusoidal, the gate-source voltage Vgs1,2 is also sinusoidal. This condition causes a non-linear characteristic of the circuit arrangement 10 when it is in the ON state, that is, turned on, and the input signal Vs1 has a high dynamic range, or rather, a high ratio between maximum and minimum amplitude, because it has a channel modulation in place in the MOSFETs due to the fluctuations of their gate-source voltage Vgs1,2 
The drain-source resistance in the ON state RDS_ON, due to the fluctuations of the gate-source voltage Vgs1,2 is subject to a non-linear variation. This causes a signal distortion on the load of the switching circuit, for example the loudspeaker.